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(R)
L9346
QUAD INTELLIGENT POWER LOW SIDE SWITCH
QUAD POWER LOWSIDE DRIVER WITH 2 x 5A AND 2 x 3A OUTPUT CURRENT CAPABILITY LOW RDSON TYPICALLY 200m AND 300m @ Tj = 25C INTERNAL OUTPUT CLAMPING STRUCTURES WITH VFB = 50V FOR FAST INDUCTIVE LOAD CURRENT RECIRCULATION LIMITED OUTPUT VOLTAGE SLEW RATE FOR LOW EMI PROTECTED P COMPATIBLE ENABLE AND INPUT WIDE OPERATING SUPPLY VOLTAGE RANGE 4.5V TO 32V REAL TIME DIAGNOSTIC FUNCTIONS: - OUTPUT SHORTED TO GND - OUTPUT SHORTED TO VSS - OPEN LOAD MEASURED IN ON AND OFF CONDITION - LOAD BYPASS DETECTION - OVERTEMPERATURE DEVICE PROTECTION FUNCTIONS: BLOCK DIAGRAM
IN1 Channel1
Power SO20
Chip
ORDERING NUMBERS: L9346PD (power SO20) L9346DIE (chip)
- OVERLOAD DISABLE - REVERSE SUPPLY VOLTAGE PROTECTED VS UP TO -2V - SELECTIVE THERMAL SHUTDOWN DESCRIPTION The L9346 is a monolithic integrated quad low side driver realized in an advanced Multipow-
OUT1 D1
EN
VS
Output Control Overtemp IN4 R Q D4 Diagnostic Control Channel4 Openload S Delay Timer Overload
52V R IO
OUT4
IN2 Channel2 OUT2 D2
IN3 Channel3 OUT3 D3
G ND
May 2000
1/13
L9346
The inputs are P compatible. Particular care has been taken to protect the device against failures, to avoid electromagnetic interferences and to offer extensive real time diagnostic.
DESCRIPTION (continued) erBCD mixed technology. The device is intended to drive valves in automotive environment. ABSOLUTE MAXIMUM RATINGS
Symbol VS VSP dVS dt VIN, EN VD VODC IO1, 2 IO3, 4 IOR1, 2 IOR3, 4 EO1, 2 EO3, 4 VGND TjEO Tj Tstg TjDIS GND Potential Difference Juntion Temperature During Switch-off Juntion Temperature Storage Temperature Thermal Disable Junction Temp. Threshold Parameter DC Supply Voltage Supply Voltage Pulse (duration <200ms) Supply Voltage Slope
Conditions
Value -2 to 32 -2 to 45 10
Unit V V V/s
Input Voltage Diagnostic DC Output Voltage DC Output Voltage DC Output Current Out 1, 2 DC Output Current Out 3, 4 Reverse Output Current Reverse Output Current Switch-off Energy for Inductive Loads
I 10mA I 50mA
-2 to 16 -0.3 to 16 -0.3 to 45 5 3 -5 -3
V V V A A A A mJ mJ V C C C C C
tEO = 250s,1) T = 5ms Tj = -40 to 150C t 30 min t 15 min
50 30 0.3 175 190 -40 to TjDIS -55 to 150 180 to 210
The device is ESD protected, tested according to MIL883C with 2KV. 1) Note : tEO is the clamping time (see fig.1)
PIN CONNECTION
H e at s in k c o n ne c te d to pin s 1, 1 0, 1 1 , 2 0
PG N D OUT1
D1
PG N D O U T4
D4
IN 4
VS NC
IN 1
EN GND
IN 3
D2
IN 2
D3
OUT2 PG N D
O U T3 PG N D
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L9346
THERMAL DATA
Symbol Rth j-c Parameter Thermal Resistance junction to case Value 3 Unit K/W
PIN FUNCTIONS
N. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name GND Out 1 D1 IN 4 VS NC IN 3 D2 Out 2 GND GND Out 3 D3 IN 2 GND EN IN 1 D4 Out 4 GND Power Grounded Output 1 (5A) Diagnostic 1 Input 4 Supply Voltage Not Connected Input 3 Diagnostic 2 Output 2 (5A) Power Ground Power Ground Output 3 (3A) Diagnostic 3 Input 2 Signal Ground Common Enable Input 1 Diagnostic 4 Output 4 (3A) Power Ground Function
Figure 1: tEO Clamping Time
VO 1 - 4 VOC L
VS
t
t EO
T
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L9346
Figure 2: Pad Position (Chipsize 4.95 x 3.88)
ESD
4/13
L9346
Pad Coordinates (Reference point X = 0, Y = 0: Center of die)
Pat opening center position Pad Nr. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Pad Name PG3 PG3 PG2 PG2 OUT2 OUT2 D2 IN3 VS IN4 D1 OUT1 OUT1 PG1 PG1 PG4 PG4 OUT4 OUT4 D4 IN1 EN GND IN2 D3 OUT3 OUT3 Test pad Gate 2 VTERM2 IOLRED ESD VTERM1 GATE1 GATE4 VTERM4 VTERM3 GATE3 Size in (m) 178 x 280 178 x 280 178 x 280 178 x 280 280 x 178 280 x 178 178 x 178 178 x 178 178 x 178 178 x 178 178 x 178 280 x 178 280 x 178 178 x 178 178 x 178 178 x 178 178 x 178 280 x 178 280 x 178 178 x 178 178 x 178 178 x 178 178 x 178 178 x 178 178 x 178 280 x 178 280 x 178 Size d = 102 d = 102 d = 102 178 x 178 d = 102 d = 102 d = 102 d = 102 d = 102 d = 102 Description Power Ground 3 Power Ground 3 Power Ground 2 Power Ground 2 Output 2 5A Output 2 5A Diagnostic 2 Input 3 Supply Voltage Input 4 Diagnostic 1 Output 1 5A Output 1 5A Power Ground 1 Power Ground 1 Power Ground 4 Power Ground 4 Output 4 3A Output 4 3A Diagnostic 4 Input 1 Common Enable Signal Ground Input 2 Diagnostic 3 Output 3 3A Output 3 3A Coordinates in (m) X 2286.5 2286.5 2286.5 2286.5 1472.5 1722.5 1036 648 -260 -648 -1036 -1722.5 -1472.5 -2286 -2286 -2286 -2286 -1448 -1656 -970 -582 -194 194 582 970 1656.5 1448.5 X 1447 1260 449.5 260 -1260 -1447 -1381 -1194.5 1194.5 1381 Y 1175 506 98 -842 -844 -1644 -1644 -1644 -1644 -1644 -1644 -1644 -844 -842 98 506 1175 865 1644 1644 1644 1644 1644 1644 1644 1644 865 Y -1612 -1600 -1455.5 -1644 -1600 -1612 1600 1600 1600 1600
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L9346
ELECTRICAL CHARACTERISTICS (Operating Range) The electrical characteristics are valid within the below defined operating range, unless otherwise specified.)
Symbol VS Tj1 Tj2
NOTE:
2)
Parameter Board Supply Voltage Junction Temperature Junction Temperature
Test Condition
Min. 4.5 -40 150
Typ. 12
Max. 32 150 TjDIS
Unit V C C
t 15min
2)
over life time
Parameters guaranteed by correlation
ELECTRICAL CHARACTERISTICS (VS = 4.5 to 32V; -40C j1 150C < Tj2 jDIS, unless otherwise specified.)
Symbol Parameter Test Condition Min. Value Tj1 Typ. Max. Value Tj2 Min. Max. Unit
Supply
IVS OFF IVS ON DC Supply Current Off DC Supply Current On EN = 1.0V VS 14V; VIN, VEN = 2V ID 3mA VD = 14V3) 5 8 10 mA mA
Diagnostic Outputs D 1 - D 4
VDL IDLE Diagnostic Output Low Voltage Diagnostic Output Leakage Current 0.65 0.1 1.0 2 1.5 20 V A
Outputs Out 1 - Out 4
VOUV 1-4 VOUV hys 1-4 VOUV 1-4,
2-3, 4-1, 3-2
Open Load Voltage Threshold Hysteresis Open Load Difference Voltage Threshold
VIN = 1V
0.525 x VS
VIN1,4/2,3 = 1V, 4.5V VOc 16V, 4.5V VS 16V, VOc = output voltage of other channel
VOC 1.0V
0.55 x 0.575 x 0.5 x VS 0.65 x VS VS VS 0.003 x VS VOC VOC VOC VOC 1.25V 1.5V 0.8V 1.7V
V V V
VOUV hys 1-4,
2-3, 4-1, 3-2
Open Load Hysteresis Open Load Current Threshold Over Load Current Threshold Output Voltage During Clamping Output (fall, rise) slew rate Internal Output Pull Down Resistor Output On Resistance VEN = VIN = 2V; VS = 6.5 to 16V VS > 6.5V; VOUT = 32V IOCL 200mA
4)
40 160 5 3 45 400 10 320 10 6 52 1500 20 200 480 4 2.4 60 2850 40 300 500 450 750 200 3500 50 580
mV mA A A V V/ms K m
IOUC 1, 2, 3, 4 IOOC 1, 2 IOOC 3, 4 VOCL SON,OFF RIO RDSON 1, 2
IOUC IO IOOC
VEN = 1V Tj = 25C Tj = 150C VS > 9.5V, IO1,2 = 2A Tj = 25C Tj = 150C; IO3,4 = 1.3A
RDSON 3, 4
300
m
NOTE: 2) Parameters guaranteed by correlation 3) The diagnostic output is short circuit protected up to VD = 16V 4) VS = 9 to 16V
6/13
L9346
ELECTRICAL CHARACTERISTICS (continued)
Symbol Parameter Test Condition Min. Value Tj1 Typ. Max. Value Tj2 Min. Max. Unit
Inputs IN1-4, EN
VIN,EN L VIN,EN H VEN,IN hys IIN IEN Logic Input/Enable Low Voltage Logic Input/Enable High Voltage Logic Input Hysteresis Input Sink Current Enable Sink Current -0.3 IN, EN 2.0 0.2 10 10 0.4 30 20 1 16 0.8 60 40 0.8 V V V A A s s s s s s s
VIN = 2 to 12V5)
240 240
Timing
tD ON tD OFF tDH-L, Diag tD IOU tDOL tD EN ON tD EN OFF
NOTE:
5) 6)
Output Delay ON Time Output Delay OFF Time Diag. Delay Output OFF Time Diagnostic Open Load Delay Time Diagnostic Overload Delay Switch-OFF Time Enable ON Time Enable OFF Time
6) 6)
Fig. 7 Fig. 7 6) Fig. 6 VS = 9 to 16V, Fig 8 IO IOUC VS = 9 to 16V, Fig 8 IO > IOOC 6) Fig. 7 6) Fig. 7
5 8
4 15
25 30 65 50 300 25 25
90
8 50 160 4 4
Open pins (EN, IN) are detected as low VS = 9 to 16V IOUC IO IOOC
DIAGNOSTIC TABLE
CONDITIONS Normal Function EN L H H GND short Load bypass Open Load Over Load VOtyp < 0.55VS VO1-4/2-3 1.25V IO1,2,3,4typ < 320mA
8)
IN X L H X L H X H
OUT off off on7) off off on7) off off DC don't care
DIAG. L L H H H L L L DC don't care
L H H X H X
Tjtyp 190C Overtemperature
IOmin 1,3 > 5A IOmin 2,4 > 3A
Reset and Overtemperature Latch
NOTE:
7) 8)
For VS = 4.5 to 6.5V, IO 2A, the diag. table is valid If one diag. status shows the overtemperature, recognition, in parallel this output will be switched OFF internally. The corresponding channel should be switched OFF additionally by its input signal, otherwise the overload latch will be set aftert DOL is passed. This behaviour is related to the overdrop sensing which is used as over load recognition. The overtemperature is latched (DIAG = L) until the level of the IN signal changes to low.
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L9346
CIRCUIT DESCRIPTION The L9346 is a quad low side driver for inductive loads like valves in automotive environment. The internal pull down current sources at the ENABLE and INPUT pins assure in case of open input conditions that the device is switched off. An output voltage slope limitation for du/dt is implemented to reduce the EMI. An integrated active flyback voltage limitation clamps the output voltage during the flyback phase to 50 V. Each driver is protected against short circuit at VOUT < 32V and thermal overload. In short circuit condition the output will be disabled after a short delay time tDOL. The thermal disable for TJ > 180C of the output will be reseted if the junction temperature decreases about 20C below the disable threshold temperature. The overtemperatureinformation is stored until IN = L. For the real time error diagnosis the voltage and the current of the outputs are compared with internal fixed values VOUV for OFF and IOUC for ON conditions to recognize open load (RL 20 K, RL > 38) in OFF and ON conditions. Also the output voltages VO1 - 4 are compared to each other output in OFF condition with a fixed Figure 3. Diagnostic Overload Delay Time
V IN
offset of VOUV to recognize load bypasses. To suppress the VOUV diagnoses during the flyback phases of the compared output, the VOUV diagnostic includes a latch function. Reaching the flyback clamping voltage VOCL the diagnostic signal is reseted by a latch. To activate again this kind of diagnostic a low signal at the correspondent INPUT or the ENABLE pin must be applied (see also Fig.3). The outputs 1 and 4 are compared for VOUV and also outputs 2 and 3 are compared. The diagnostic output level in connection with different ENABLE and INPUT conditions allows to recognize different fail states, like overtemp, short to VSS, short to GND, bypass to GND and disconnected load (see diagnostic table). The diagnostic output is protected against short circuit. Exceeding the over load current threshold IOOC, the output current will be limited internally during the diagnostic overload delay switch-off time tDOL. The device complies the ISO pulses imposed to the supply voltage of the valves without any failures of the functionality.
5V
t
IO
I OOL
5A 3A I OUC t t DOL
VD
5V
t
8/13
L9346
Figure 4. OUTPUT SLOPE (Resistive load for testing)
V IN
5V V
(EN)H V (EN)L t t D ON V tD E N O N OUT t D OFF tD E N O F F
VS 0.85 VS VO U V 0.15 VS t S ON S OFF 0.85VS
V
DIAG V
D
0.5 V
D
t
t D H -L D ia g
Figure 5. TIMING (tDENON, tDON, tDENOFF, tDOFF)
E N , IN VO N
0.85 x VO UT 0.15 x V O U T
t DE N OFF , t DO FF
t D EN ON , t D O N
9/13
L9346
Figure 6. TIMING (tDOL, tDIOU)
IN VON
I OOC
I OUC
VD t DIOU t DOL
Open load current
Figure 7. BLOCK DIAGRAM - Open Load Voltage Detection
V Batt.
L1 (L2) OUT1 ( OU T2) OUT4 (OU T3)
L4 (L3)
IN 1
IN 4
R IO
R IO
VS
55%
-
+
+
-
Enable
&
R S
&
Latch
Q
R
S
Latch
Q
&
V O UV 1
&
V O U V4
10/13
L9346
Figure 8. Logic Diagram
V EN
V
IN
VO u
IO o
IO u
V
D
op e n lo ad c u rren t
la tc h re se t
c urrent
op en lo ad v o lt ag e
nor ma l opera tion ON
o p en l oa d
latched o ve r. load di agno stic
op e n lo ad cu rren t
nor ma l ope ration ON
nor ma l operation O FF
o p e n lo a d v o lta g e
Figure 9. Application Circuit Diagram
+5V
VCC I/O I/O
IN 1 C ha nne l 1 OUT1 D1
Z VALVE
I/O
KL 15
EN
VS
+45V
O ut pu t C o ntr ol
I/O +5V
52 V R IO
OUT4
Z VALVE
KL 30 V Batt
Ov er tem p IN 4 R Q S D e la y T im e r
O v erlo a d
I/O
D4
P Controller
D iagn o s tic C o ntr ol C ha nne l 4
+5V
O p enloa d
IN 2
I/O
Z VALVE
C ha nne l 2
I/O
OUT2 D2
+5V
IN 3
I/O
Z VALVE
C ha nne l 3
I/O
OUT3 D3
GND
GND
11/13
L9346
mm TYP. inch TYP.
DIM. A a1 a2 a3 b c D (1) D1 E e e3 E1 (1) E2 E3 G H h L N S T
MIN. 0.1 0 0.4 0.23 15.8 9.4 13.9
MAX. 3.6 0.3 3.3 0.1 0.53 0.32 16 9.8 14.5
MIN. 0.004 0.000 0.016 0.009 0.622 0.370 0.547
MAX. 0.142 0.012 0.130 0.004 0.021 0.013 0.630 0.386 0.570
OUTLINE AND MECHANICAL DATA
1.27 11.43 10.9 5.8 0 15.5 0.8 11.1 0.429 2.9 6.2 0.228 0.1 0.000 15.9 0.610 1.1 1.1 0.031 10 (max.) 8 (max.) 10
0.050 0.450 0.437 0.114 0.244 0.004 0.626 0.043 0.043
JEDEC MO-166
0.394
(1) "D and F" do not include mold flash or protrusions. - Mold flash or protrusions shall not exceed 0.15 mm (0.006"). - Critical dimensions: "E", "G" and "a3"
PowerSO20
N
N a2 b e A
R
c DETAIL B a1 E DETAIL A
DETAIL A e3 H
lead
D a3 DETAIL B
20 11
Gage Plane 0.35
slug
-C-
S E2 T E1 BOTTOM VIEW
L
SEATING PLANE GC (COPLANARITY)
E3
1 10
h x 45
PSO20MEC
D1
12/13
L9346
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2000 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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